Examples


Vexriscv in a Simulation (Verilator)


HELLO WORLD EXAMPLE:

With this example you can do:

  • Build a Vexriscv CPU from SpinalHDL to Verilog.
  • Run the Vexriscv in a Simulation with Verilator.
  • Compile a C application to an ELF file.
  • Upload the ELF file to the Vexriscv CPU with OpenOCD and Risc-V GDB.
  • See the output of the C application (hello world).
  • Step through the C application with GDB.

In a nutshell: A full Vexriscv in a Simulation including a C demo-application (hello world).

Link to the project on GitHub:

https://github.com/ThorKn/vexriscv-sim-helloworld

Usage:

Clone the project into the Virtual Machine and follow the instructions in the README of the project.


CUSTOM INSTRUCTION EXAMPLE (SIMPLE_PLUGIN):

With this example you can do:

  • Build a Vexriscv CPU from SpinalHDL to Verilog, including a new custom Instruction for the RISC-V ISA.
  • Run the Vexriscv in a Simulation with Verilator.
  • Compile a C application to an ELF file, including the usage of the new custom instruction.
  • Upload the ELF file to the Vexriscv CPU with OpenOCD and Risc-V GDB.
  • See the output of the C application.
  • Step through the C application with GDB.

In a nutshell: A full Vexriscv in a Simuation including a custom instruction and a C demo-application.

Link to the project on GitHub:

https://github.com/ThorKn/vexriscv-sim-simple-plugin

Usage:

Clone the project into the Virtual Machine and follow the instructions in the README of the project.


Vexriscv on a Radiona ULX3S FPGA Board


HELLO WORLD EXAMPLE:

With this example you can do:

  • Build a Vexriscv CPU from SpinalHDL to Verilog.
  • Generate a Bitstream of the Vexriscv for the ULX3S Board.
  • Flash the Bitstream to the ULX3S Board.
  • Compile a C application to an ELF file.
  • Upload the ELF file to the Vexriscv CPU with OpenOCD and Risc-V GDB.
  • Connect a serial terminal via UART to see the output of the C application (hello world).
  • Step through the C application with GDB.

In a nutshell: A full Vexriscv on a FPGA including a C demo-application (hello world).

Link to the project on GitHub:

https://github.com/ThorKn/vexriscv-ulx3s-helloworld

Usage:

Clone the project into the Virtual Machine and follow the instructions in the README of the project.


CUSTOM INSTRUCTION EXAMPLE (SIMPLE_PLUGIN):

With this example you can do:

  • Build a Vexriscv CPU from SpinalHDL to Verilog, including a new custom Instruction for the RISC-V ISA.
  • Generate a Bitstream of the Vexriscv for the ULX3S Board.
  • Flash the Bitstream to the ULX3S Board.
  • Compile a C application to an ELF file, including the usage of the new custom instruction.
  • Upload the ELF file to the Vexriscv CPU with OpenOCD and Risc-V GDB.
  • Connect a serial terminal via UART to see the output of the C application.
  • Step through the C application with GDB.

In a nutshell: A full Vexriscv on a FPGA including a custom instruction and d C demo-application.

Link to the project on GitHub:

https://github.com/ThorKn/vexriscv-ulx3s-simple-plugin

Usage:

Clone the project into the Virtual Machine and follow the instructions in the README of the project.